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MOSEL VITELIC
V53C806H HIGH PERFORMANCE 1M x 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 23 ns 75 ns
45
45 ns 22 ns 25 ns 80 ns
50
50 ns 24 ns 28 ns 90 ns
60
60 ns 30 ns 40 ns 120 ns
Features
s 1M x 8-bit organization s Fast Page Mode for a sustained data rate of 43 MHz s RAS access time: 40, 45, 50, 60 ns s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Refresh Interval: 1024 cycle/16 ms s Available in 28-pin 400 mil SOJ package s Single +5V 10% Power Supply s TTL Interface
Description
The V53C806H is a ultra high speed 1,048,576 x 8 bit CMOS dynamic random access memory. The V53C806H offers a combination of features: Fast Page Mode for high data bandwidth, and Low CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 1024 x 8 bits within a row with cycle times as fast as 23 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements. The V53C806H is ideally suited for graphics, digital signal processing and high-performance computing systems.
Device Usage Chart
Operating Temperature Range 0C to 70 C Package Outline K * 40 * Access Time (ns) 45 * 50 * 60 * Power Std. * Temperature Mark Blank
V53C806H Rev. 1.6 April 1998
1
MOSEL VITELIC
V 5 3 C 8 0 6 H
V53C806H
FAMILY
DEVICE K (SOJ)
PKG
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL)
Description SOJ
Pkg. K
Pin Count 28
40 45 50 60
(40 ns) (45 ns) (50 ns) (60 ns)
808H-01
28-Pin SOJ PIN CONFIGURATION Top View
VCC IO1 IO2 IO3 IO4 WE RAS NC NC A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
806H-02
Pin Names
A0-A9 RAS Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
V SS IO8 IO7 IO6 IO5 CAS OE A9 A8 A7 A6 A5 A4 VSS
CAS WE OE I/O1-I/O8 VCC VSS NC
Absolute Maximum Ratings*
Ambient Temperature Under Bias..................................-10C to +80C Storage Temperature (plastic)......-55C to +125C Voltage Relative to VSS .................-1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation.......................................... 1.4 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
TA = 25C, VCC = 5 V 10%, f = 1 MHz
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
Capacitance*
* Note: Capacitance is sampled and not 100% tested
V53C806H Rev. 1.6 April 1998
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MOSEL VITELIC
Block Diagram
1M x 8
OE WE CAS RAS
V53C806H
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0 -Y9
I/O1 I/O2 I/O3
I/O BUFFER
SENSE AMPLIFIERS
1024 x 8
REFRESH COUNTER
10 A0 A1
I/O4 I/O5 I/O6 I/O7 I/O8
ADDRESS BUFFERS AND PREDECODERS
X 0 -X9
ROW DECODERS
1024
* * *
A8 A9
MEMORY ARRAY 1024 x 1024 x 8
806H-03
V53C806H Rev. 1.6 April 1998
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MOSEL VITELIC
DC and Operating Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified.
Access Time V53C806H Min.
-10
V53C806H
Symbol
ILI ILO ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Typ.
Max.
10
Unit
mA mA mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
40 45 50 60
220 210 200 190 4
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 40 45 50 60
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
220 210 200 190 110 100 90 80 2.0
mA
ICC4
VCC Supply Current, Fast Page Mode Operation
40 45 50 60
mA
Minimum cycle
1, 2
ICC5 ICC6
VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby
mA
RAS = VIH, CAS = VIL other inputs VSS RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS
1
2.0
mA
VCC VIL VIH VOL VOH
Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
4.5 -1 2.4
5.0
5.5 0.8 VCC + 1 0.4
V V V V V IOL = 4.2 mA IOH = -5 mA 3 3
2.4
V53C806H Rev. 1.6 April 1998
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AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
40 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address CAS to Low-Z Output Output buffer turn-off delay time Column Address Hold Time from RAS RAS to Column Address Delay Time 25 tRSH (W) tCWL tWCS tWCH tWP RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width 12 13 14 15 0 0 30 6 Min. 40 75 25 40 12 17 0 0 7 0 5 12 5 0 28 Max. 75K Min. 45 80 25 45 13 18 0 0 8 0 6 13 5 0 32 45 Max. 75K Min. 50 90 30 50 14 19 0 0 9 0 7 14 5 0 36 50 Max. 75K Min. 60 110 40 60 15 20 0 0 10 0 10 15 5 0 43 60 Max. 75K
V53C806H
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
4
5
15
0
0
0
0
ns
5
16 17 18 19 20 21 22 23
8 12 12 40 20
9 13 13 45 22 0 0 35 7
10 14 14 50 24 0 0 40 8
10 17 17 60 30 0 0 45 10
ns ns ns ns ns ns ns ns 6, 7 6, 8, 9 6, 7, 10 16 16
24
12
20
13
23
14
26
15
30
ns
11
ns
26 27 28 29
12 0 5 5
13 0 6 6
14 0 7 7
15 0 10 10
ns ns ns ns 12, 13
V53C806H Rev. 1.6 April 1998
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AC Characteristics (Cont'd)
40 # 30 Symbol tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF Parameter Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in Read-ModifyWrite Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh Fast Page Mode Read-Modify-Write Cycle Time Transition Time (Rise and Fall) Refresh Interval (1024 Cycles) 30 Min. 30 Max. Min. 35 45 Max. Min. 40 50 Max. Min. 45 60 Max.
V53C806H
Unit ns
Notes
31 32 33 34 35 36 37
12 0 5 6 6 110 75
13 0 6 7 7 115 80
14 0 7 8 8 130 87
15 0 10 10 10 170 105
ns ns ns ns ns ns ns 14 14 14 14
38 39
30 58
32 62
34 68
40 85
ns ns
12 12
40 41 42
48 38 23
50 41 25
52 42 28
65 58 40
ns ns ns 12
43 44
5 20
6 22
7 24
8 30
ns ns
45
23
25
27
34
ns
7
46
35
40
50
ns
47
10
10
10
10
ns
48 49
0 8
0 10
0 12
0 15
ns ns
50
60
65
70
85
ns
51 52
3
50 16
3
50 16
3
50 16
3
50 16
ns ms
15
V53C806H Rev. 1.6 April 1998
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Notes:
V53C806H
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to two TTL inputs and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns . 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C806H Rev. 1.6 April 1998
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Waveforms of Read Cycle
t RAS (1) t RC (2) t RP (3)
V53C806H
RAS
VIH VIL t CRP (13)
t AR (23)
t RCD (6) t RAD (24)
t CSH (4)
CAS
VIH VIL t ASR (8) t RAH (9)
t RSH (R)(12) t CAS (5)
t CRP (13)
t ASC (10)
t CAH (11)
ADDRESS
VIH VIL
ROW ADDRESS
COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15)
t RCS (7) WE VIH VIL
t ROH (16) t CAA (20) t HZ (22) t OAC (17) t CAC (18) t HZ (22) VALID DATA-OUT t LZ (21)
806H-04
OE
VIH VIL t RAC (19)
t HZ (22)
I/O
VOH VOL
Waveforms of Early Write Cycle
t RAS (1) t RC (2) t RP (3)
RAS
V IH V IL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS
V IH V IL t RAH (9)
t RSH (W)(25) t CAS (5)
t CRP (13)
t ASR (8) ADDRESS V IH V IL ROW ADDRESS
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS t WCH (28)
t RAD (24)
WE
V IH V IL
t WP (29) t WCS (27)
t CWL (26)
t WCR (30) V IH V IL t DS (32) I/O V IH V IL t DHR (46)
t RWL (31)
OE
t DH (33) HIGH-Z
806H-05
VALID DATA-IN
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
8
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t AR (23) t RAS (1) t RC (2) t RP (3)
V53C806H
RAS
V IH V IL t CRP (13)
t RCD (6)
t CSH (4)
CAS
V IH V IL t RAD (24) t RAH (9)
t RSH (W)(12) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
t ASR (8) ADDRESS V IH V IL
ROW ADDRESS
COLUMN ADDRESS t CWL (26) t RWL (31)
t WP (29) WE V IH V IL
t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN
806H-06
I/O
Waveforms of Read-Modify-Write Cycle
tRRW (37) t RWC (36) t RP (3)
RAS
VIH VIL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS
VIH VIL t RAH (9) t ASR (8) VIH VIL ROW ADDRESS t RAD (24) VIH VIL VIH VIL t CAA (20) t OAC (17) t t ASC (10) COLUMN ADDRESS
t RSH (W)(25) t CRW (40)
t CRP (13)
CAH (11)
ADDRESS
t RWD (39) t RCS (17)
t AWD (41) t CWD (38)
t RWL (31)
t CWL (26)
t WP (29)
WE
OE
t OED (35) t CAC (18) t RAC (19) I/O VIH VOH VIL VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN
t DH (33)
806H-07
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
9
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
VIH V IL t RCD (6) tCRP (13) CAS VIH V IL t RAH (9) tCSH (4) tASC (10) t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t RCH (14) t CAH (11) t RCS (7) COLUMN ADDRESS t RCS (7) tCAR (44) t CAH (11) tPC (42) tCP(43) tRSH (R)(12) tCAS (5) t CRP (13) t CAS (5) tAR (23) t RAS (1)
V53C806H
t
RP (3)
RAS
t CAS (5)
tASR (8) ADDRESS VIH V IL
tASC (10) ROW ADDRESS t RCS (7)
tRCH (14)
WE
VIH V IL tCAA (20) t OAC (17) t CAP (45) t OAC (17) t CAA (20) t OAC (17) tRRH (15)
OE
VIH V IL tHZ (22) tRAC (19) tCAC (18) t LZ (21) t CAC (18) t HZ (22) t LZ (21) t LZ (21) tHZ (22) tHZ (22) V ALID DATA OUT VALID DATA OUT
806H-08
t CAC (18)
tHZ (22) tHZ (22)
I/O
VOH VOL
VALID DATA OUT
Waveforms of Fast Page Mode Write Cycle
tAR (23) RAS V IH V IL t CRP (13) tRCD (6) CAS V IH V IL tCSH (4) tRAH (9) tASR (8) V IH ADDRESS V IL tRAD (24) tWCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32) I/O V IH V IL VALID DATA IN tDS (32) tDH (33) OPEN VALID DATA IN tDS (32) tDH (33) VALID DATA IN tDH (33) OPEN
806H-09
tRP (3) t RAS (1)
t PC (42) t CP(43) t CAS (5)
tRSH (W)(25) tCRP (13) tCAS (5) tCAS (5)
tCAR (44) tASC (10) tCAH (1 1) tASC (10) tCAH (11) COLUMN ADDRESS t CWL (26) tWCS (27) t WCH (28) t WCS (27) t WCH (28) t WP(29) tRWL(31) t WCH (28) tWP(29) COLUMN ADDRESS tCWL (26) t CAH (1 1)
ROW ADD
COLUMN ADDRESS t CWL (26)
OE
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
10
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS VIH V
IL
V53C806H
t RASP (37)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V CAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RCS (7) V WE V
IH IL
t RWD (39) t CWD (38)
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t CAA (20)
t CAP (43)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN
806H-10
IN
t LZ (21)
t LZ (21)
Waveforms of RAS-Only Refresh Cycle
t RC (2) V IH V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADDR
806H-11
t RAS (1)
t RP (3)
RAS
t RAH (9)
WE, OE = Don't care
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
11
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS V IH V IL t CSR (47) CAS V IH V IL V IH V IL READ CYCLE V IH V IL t ROH (16) t OAC (17) OE V IH V IL t LZ (21) I/O V IH V IL WRITE CYCLE t WCS (27) WE V IH V IL V IH V IL t DS (32) I/O V IH V IL t DH (33) D IN t RWL (31) t CWL (26) t WCH (28) DOUT t CHR (49) t CP (43) t RSH (W)(25) t CAS (5)
V53C806H
t RP (3)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
WE
t HZ (22) t HZ (22)
t HZ (22)
OE
806H-12
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A 0 -A 9 = Don't care
806H-13
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
12
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O V OH V OL VALID DATA t HZ (22) t HZ (22) t OAC (17) t HZ (22)
ROW ADD
V53C806H
t RAS (1) t AR (23)
tRP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t RCS (7) WE
t RRH (15)
OE
806H-14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL V IH OE V IL t DS (32) I/O V IH V IL t DH (33)
VALID DATA-IN ROW ADD
t RAS (1) t AR (23)
t RP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t WCS (27) WE
t WCH (28)
t DHR (46)
806H-15
Don't Care
V53C806H Rev. 1.6 April 1998
Undefined
13
MOSEL VITELIC
Functional Description
The V53C806H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C806H reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C806H
Fast Page Mode Operation
Fast Page Mode operation permits all 1024 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides a sustained data rate of 43 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 1024 Data Rate = ------------------------------------------t RC + 1023 t PC
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Data Output Operation
The V53C806H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition enables the internal I/O path. A CAS high transition or RAS high transition, whichever occurs later, disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal
V53C806H Rev. 1.6 April 1998
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MOSEL VITELIC
has no effect on any data stored in the output latches. A WE low level can also disable the output drivers. During a Write cycle, if WE goes low at a time when the CAS is low, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. To retain data, 1024 Refresh Cycles are required in each 16 ms period. There are two ways to refresh the memory: 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any Read, Write, Read-Modify-Write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CAS-before-RAS refresh is activated. The V53C806H uses the output of an internal 10-bit counter as the source of row addresses and ignore external address inputs. CAS-before-RAS is a "refresh-only" mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter.
V53C806H
Power-On
After application of the VCC supply, an initial pause of 200 ms is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C806H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
Table 1. V53C806H Data Output
Operation for Various Cycle Types
Cycle Type Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Read-Modify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles I/O State Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycles High-Z
Data Retention Mode
The V53C806H offers a CMOS standby mode that is entered by causing the RAS clock to swing between a valid VIL and an "extra high" VIH within 0.2 V of VCC. While the RAS clock is at the extra high level, the V53C806H power consumption is reduced to the low ICC6 level. Overall ICC consumption when operating in this mode can be calculated as follows: ( t RC ) ( I CC1 ) + ( t RX - t RC ) ( I CC6 ) I = ----------------------------------------------------------------------------------------------t RX Where: tRC = Refresh Cycle Time tRX = Refresh Interval/1024
V53C806H Rev. 1.6 April 1998
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MOSEL VITELIC
Package Diagrams
28-Pin Plastic SOJ
V53C806H
Unit in inches [mm] 0.725 0.005 [18.42 0.12] 28 15
0.400 0.005 [10.16 .0.13]
0.440 0.005 [11.18 0.12]
1
14
+0.007 0.138 -0.006 0.028 +0.102 +0.004 0.711 -0.051 -0.002 3.51 +0.178 -0.154
0.043 MAX [1.09 MAX] 0.004 [0.102] 0.05 bsc [1.27 bsc] 0.015/0.020 [0.38/0.51] 0.025 MIN [.635 MIN]
V53C806H Rev. 1.6 April 1998
16
0.370 0.010 [9.40 0.26]
MOSEL VITELIC
V53C806H
V53C806H Rev. 1.6 April 1998
17
MOSEL VITELIC
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V53C806H
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(c) Copyright 1997, MOSEL VITELIC Inc.
4/98 Printed in U.S.A.
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MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
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